DMA channel configurationA DMA channel needs to be configured, these functions provide handy helpers to set up configuration structures. See dma_channel_config. More...

Functions

static void channel_config_set_read_increment (dma_channel_config *c, bool incr)

Set DMA channel read increment in a channel configuration object. More...

static void channel_config_set_write_increment (dma_channel_config *c, bool incr)

Set DMA channel write increment in a channel configuration object. More...

static void channel_config_set_dreq (dma_channel_config *c, uint dreq)

Select a transfer request signal in a channel configuration objectThe channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ 0x3b -> Select Timer 0 as TREQ 0x3c -> Select Timer 1 as TREQ 0x3d -> Select Timer 2 as TREQ (Optional) 0x3e -> Select Timer 3 as TREQ (Optional) 0x3f -> Permanent request, for unpaced transfers. More...

static void channel_config_set_chain_to (dma_channel_config *c, uint chain_to)

Set DMA channel chain_to channel in a channel configuration objectWhen this channel completes, it will trigger the channel indicated by chain_to. Disable by setting chain_to to itself (the same channel) More...

static void channel_config_set_transfer_data_size (dma_channel_config *c, enum dma_channel_transfer_size size)

Set the size of each DMA bus transfer in a channel configuration objectSet the size of each bus transfer (byte/halfword/word). The read and write addresses advance by the specific amount (1/2/4 bytes) with each transfer. More...

static void channel_config_set_ring (dma_channel_config *c, bool write, uint size_bits)

Set address wrapping parameters in a channel configuration objectSize of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15) More...

static void channel_config_set_bswap (dma_channel_config *c, bool bswap)

Set DMA byte swapping config in a channel configuration objectNo effect for byte data, for halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse their order. More...

static void channel_config_set_irq_quiet (dma_channel_config *c, bool irq_quiet)

Set IRQ quiet mode in a channel configuration objectIn QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. More...

static void channel_config_set_high_priority (dma_channel_config *c, bool high_priority)

Set the channel priority in a channel configuration objectWhen true, gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. More...

static void channel_config_set_enable (dma_channel_config *c, bool enable)

Enable/Disable the DMA channel in a channel configuration objectWhen false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) More...

static void channel_config_set_sniff_enable (dma_channel_config *c, bool sniff_enable)

Enable access to channel by sniff hardware in a channel configuration objectSniff HW must be enabled and have this channel selected. More...

static dma_channel_config dma_channel_get_default_config (uint channel)

Get the default channel configuration for a given channel

Setting	Default
Read Increment	true
Write Increment	false
DReq	DREQ_FORCE
Chain to	self
Data size	DMA_SIZE_32
Ring	write=false, size=0 (i.e. off)
Byte Swap	false
Quiet IRQs	false
High Priority	false
Channel Enable	true
Sniff Enable	false

More...

static dma_channel_config dma_get_channel_config (uint channel)

Get the current configuration for the specified channel. More...

static uint32_t channel_config_get_ctrl_value (const dma_channel_config *config)

Get the raw configuration register from a channel configuration. More...

Detailed Description

DMA channel configuration

A DMA channel needs to be configured, these functions provide handy helpers to set up configuration structures. See dma_channel_config.

Function Documentation

◆ channel_config_get_ctrl_value()

static uint32_t channel_config_get_ctrl_value ( const dma_channel_config * config )

inlinestatic

Get the raw configuration register from a channel configuration.

Parameters

config Pointer to a config structure.

Returns: Register content

◆ channel_config_set_bswap()

static void channel_config_set_bswap	(	dma_channel_config *	c,
		bool	bswap
	)

inlinestatic

Set DMA byte swapping config in a channel configuration objectNo effect for byte data, for halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse their order.

Parameters

c	Pointer to channel configuration object
bswap	True to enable byte swapping

◆ channel_config_set_chain_to()

static void channel_config_set_chain_to	(	dma_channel_config *	c,
		uint	chain_to
	)

inlinestatic

Set DMA channel chain_to channel in a channel configuration objectWhen this channel completes, it will trigger the channel indicated by chain_to. Disable by setting chain_to to itself (the same channel)

Parameters

c	Pointer to channel configuration object
chain_to	Channel to trigger when this channel completes.

◆ channel_config_set_dreq()

static void channel_config_set_dreq	(	dma_channel_config *	c,
		uint	dreq
	)

inlinestatic

Select a transfer request signal in a channel configuration objectThe channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ 0x3b -> Select Timer 0 as TREQ 0x3c -> Select Timer 1 as TREQ 0x3d -> Select Timer 2 as TREQ (Optional) 0x3e -> Select Timer 3 as TREQ (Optional) 0x3f -> Permanent request, for unpaced transfers.

Parameters

c	Pointer to channel configuration data
dreq	Source (see description)

◆ channel_config_set_enable()

static void channel_config_set_enable	(	dma_channel_config *	c,
		bool	enable
	)

inlinestatic

Enable/Disable the DMA channel in a channel configuration objectWhen false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

Parameters

c	Pointer to channel configuration object
enable	True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data.

◆ channel_config_set_high_priority()

static void channel_config_set_high_priority	(	dma_channel_config *	c,
		bool	high_priority
	)

inlinestatic

Set the channel priority in a channel configuration objectWhen true, gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.

Parameters

c	Pointer to channel configuration object
high_priority	True to enable high priority

◆ channel_config_set_irq_quiet()

static void channel_config_set_irq_quiet	(	dma_channel_config *	c,
		bool	irq_quiet
	)

inlinestatic

Set IRQ quiet mode in a channel configuration objectIn QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

Parameters

c	Pointer to channel configuration object
irq_quiet	True to enable quiet mode, false to disable.

◆ channel_config_set_read_increment()

static void channel_config_set_read_increment	(	dma_channel_config *	c,
		bool	incr
	)

inlinestatic

Set DMA channel read increment in a channel configuration object.

Parameters

c	Pointer to channel configuration object
incr	True to enable read address increments, if false, each read will be from the same address Usually disabled for peripheral to memory transfers

◆ channel_config_set_ring()

static void channel_config_set_ring	(	dma_channel_config *	c,
		bool	write,
		uint	size_bits
	)

inlinestatic

Set address wrapping parameters in a channel configuration objectSize of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15)

0x0 -> No wrapping.

Parameters

c	Pointer to channel configuration object
write	True to apply to write addresses, false to apply to read addresses
size_bits	0 to disable wrapping. Otherwise the size in bits of the changing part of the address. Effectively wraps the address on a (1 << size_bits) byte boundary.

◆ channel_config_set_sniff_enable()

static void channel_config_set_sniff_enable	(	dma_channel_config *	c,
		bool	sniff_enable
	)

inlinestatic

Enable access to channel by sniff hardware in a channel configuration objectSniff HW must be enabled and have this channel selected.

Parameters

c	Pointer to channel configuration object
sniff_enable	True to enable the Sniff HW access to this DMA channel.

◆ channel_config_set_transfer_data_size()

static void channel_config_set_transfer_data_size	(	dma_channel_config *	c,
		enum dma_channel_transfer_size	size
	)

inlinestatic

Set the size of each DMA bus transfer in a channel configuration objectSet the size of each bus transfer (byte/halfword/word). The read and write addresses advance by the specific amount (1/2/4 bytes) with each transfer.

Parameters

c	Pointer to channel configuration object
size	See enum for possible values.

◆ channel_config_set_write_increment()

static void channel_config_set_write_increment	(	dma_channel_config *	c,
		bool	incr
	)

inlinestatic

Set DMA channel write increment in a channel configuration object.

Parameters

c	Pointer to channel configuration object
incr	True to enable write address increments, if false, each write will be to the same address Usually disabled for memory to peripheral transfers

◆ dma_channel_get_default_config()

static dma_channel_config dma_channel_get_default_config ( uint channel )

inlinestatic

Get the default channel configuration for a given channel

Setting	Default
Read Increment	true
Write Increment	false
DReq	DREQ_FORCE
Chain to	self
Data size	DMA_SIZE_32
Ring	write=false, size=0 (i.e. off)
Byte Swap	false
Quiet IRQs	false
High Priority	false
Channel Enable	true
Sniff Enable	false

Parameters

channel DMA channel

Returns: the default configuration which can then be modified.

◆ dma_get_channel_config()

static dma_channel_config dma_get_channel_config ( uint channel )

inlinestatic

Get the current configuration for the specified channel.

Parameters

channel DMA channel

Returns: The current configuration as read from the HW register (not cached)